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? semiconductor components industries, llc, 2008 march, 2008 - rev. 1 1 publication order number: ncp590/d ncp590 dual output, high accuracy, ultra low dropout cmos ldo the ncp590 is a family of very high precision dual-output cmos ldos offered in a 2x2 dfn8 package. each output is capable of delivering up to 300 ma and is available in voltages from 0.8 v to 5 v. the set point output voltage is accurate to within 0.9% with an operating voltage input up to 5.5 v. with its ultra low dropout characteristics and low quiescent and ground current consumption, the ncp590 is ideal for all battery operated consumer and microprocessor applications. the ncp590 is protected against short circuit and thermal overload conditions. features ? dual outputs, each supporting up to 300 ma current ? available in output combinations ranging from 0.8 v to 5.0 v ? 2.1 v to 5.5 v v cc operating supply range ? ultra-high accuracy (0.9% max at 100 ma load & 25 c) ? each output has a dedicated enable control pin ? enable threshold supports sub-1 v systems ? very low drop out voltage (50 mv typ @ 100 ma load) ? low noise (~20 v rms ) without bypass capacitor ? ultra low shutdown current (0.2 a) ? low quiescent and ground current (80 - 100 a typ.) ? thermal shutdown and current limit protection ? active output discharge when disabled ? no minimum output current required for stability ? requires c out of only 1.0 f (any esr) for stability ? stable with any type of capacitor (including mlcc) and zero load ? input under voltage lock out (uvlo) ? internally compensated regulator for quick transient response ? space-efficient 2x2 dfn8 package ? this is a pb-free device applications ? cellular phones ? cameras ? mp3/cd players, pda's, camcorders ? dsp supplies ? portable info-tronics ? pcmcia cards ? networking systems, dsl/cable modems dfn8, 2x2 mn suffix case 506aa http://onsemi.com marking diagram see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information 1 xx = specific device code m = date code xx m 14 pin connections (top view) v in en1 en2 nc v out1 v out2 gnd nc 8 7 6 5 1 2 3 4
ncp590 http://onsemi.com 2 figure 1. typical application ncp590 v in v in en1 en2 nc on off on off c in 1 f v out1 v out2 gnd nc c out1 1 f c out2 1 f v out1 v out2 r load r load pin function pin no. symbol function 1 v in input; bypass directly at the ic with a 1 f ceramic capacitor to ground 2 en1 enable for output regulator 1; raise above 0.95 v to enable v out1 3 en2 enable for output regulator 2; raise above 0.95 v to enable v out2 4, 5 nc nc; do not make connection to these pins 6 gnd ground pad gnd the thermal pad should be connected to ground for best thermal performance. float if necessary 7 v out2 output 2; bypass to gnd with a capacitor, 4.7 f c 0.7 f, any esr 8 v out1 output 1; bypass to gnd with a capacitor, 4.7 f c 0.7 f, any esr figure 2. block diagram current limit saturation sense thermal protection error amplifier programmable reference + - current limit saturation sense thermal protection error amplifier + - vout2 vout1 gnd v in en1 en2
ncp590 http://onsemi.com 3 absolute maximum ratings t j = -40 c to 125 c pin symbol, parameter symbol condition min max unit v in , input to regulator voltage v in -0.3 6.0 v current i in - internally limited v in , input peak transient voltage to regulator wrt gnd v in 7.0 v v out1 , v out2 , regulated output voltage v out -0.3 v in + 0.3 or 6.0 (note 1) v current i out - internally limited en1, en2, enable input v en -0.3 v in + 0.3 or 6.0 (note 1) v junction t emperature storage t emperature t j t stg - -50 125 150 c esd capability, human body model (note 3) esd hb -2 2 kv esd capability, machine model (note 3) esd mm -200 200 v v outx -v in (note 2) v rb - 0.3 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. which ever limit is lower 2. exceeding this value will turn on the body diode of the pmos driver (reference figure 2). thermal resistance parameter symbol condition value unit junction-to-ambient 2x2 dfn 1 oz cu ja 207.0 sq mm 1 oz cu 54.2 sq mm 1 oz cu 20.2 sq mm 1 oz cu 158 210 375 c/w junction-to-ambient 2x2 dfn 2 oz cu ja 207.0 sq mm 2 oz cu 54.2 sq mm 2 oz cu 20.2 sq mm 2 oz cu 133 184 330 c/w junction-to-board 2x2 dfn psi jb 36.4 c/w lead temperature soldering, (note 4) reflow (smd styles only), lead free t sld 60 -150 sec above 217 40 sec max at peak 265 pk c moisture sensitivity level msl 1 3. this device series incorporates esd protection and is tested by the following methods: esd hbm tested per aec-q100-002 (eia/jesd22-a114) esd mm tested per aec-q100-003 (eia/jesd22-a115) 4. per ipc/jedec j-std-020c
ncp590 http://onsemi.com 4 electrical characteristics -40 c t a 85 c (note 5); v in = v out +0.5 v or 2.1 v, whichever is greater (note 6). v en1,2 = 0.95 v, c in = c out1,2 = 1.0 f, unless noted otherwise parameter symbol test conditions min typ max unit regulators input v oltage v in ** which ever limit is greater v out(max) + 0.5 or 2.1 v** - 5.5 v enable input v oltage v en * which ever limit is lower 0.0 - v in + 0.3 or 5.5* v voltage accuracy v out i out = 100 ma, t a = 25 c (note 11) -0.9 - +0.9 % voltage accuracy v out i out = 1 ma to 200 ma -40 c t a 85 c (notes 9, 11, 12) -1.9 - +1.9 % overall voltage accuracy v out i out = 1 ma to 200 ma, v in = (v out +0.5 v) to 5.5 v, 2.1 v inmin 0 c t a 85 c, (notes 12, 13) -2.4 - +2.4 % line regulation (note 7) v out i out = 1.0 ma v in = (v out + 0.5 v) to 5.5 v, v inmin = 2.1 v - 0.05 - %/v load regulation (note 7) v out i out = 1 ma to 200 ma -0.012 -0.005 0.012 %/ma drop-out voltage, (note 8) v do i out = 50 ma - 23 40 mv drop-out voltage, (note 8) v do i out = 100 ma - 52 85 mv drop-out voltage, (note 8) v do i out = 150 ma - 80 125 mv drop-out voltage, (note 8) v do i out = 200 ma - 110 170 mv drop-out voltage, (note 8) v do i out = 300 ma - 165 225 mv quiescent current; i q = i in C i out i q v en1 = 0.95 v, i out1 = 0 ma; v en2 = 0.4 v, i out2 = 0 ma or v en2 = 0.95 v, i out2 = 0 ma; v en1 = 0.4 v, i out1 = 0 ma one regulator on; one regulator off - 80 125 a quiescent current; i q = i in C i out i q i out1 = i out2 = 0 ma both regulators on - 115 195 a 5. performance guaranteed over specified operating range by design, guard banded test limits, and/or characterization. productio n tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible . 6. v out based on the greater of the two outputs. 7. overall accuracy specified over specified operating conditions of line, load, and temperature. 8. drop out voltage v do = v in C v out measured when the output voltage has dropped 100 mv from the nominal value for v out > 2.0 v. 9. guaranteed by design, not production tested. 10. regulated and stable output over full load range down to 0 ma load. 11. v in is set at v in = ((v out + 0.5 v) + 5.5 v) / 2 or v in = ((2.1 v) + 5.5 v) / 2, whichever is greater. 12. applicable for v out 1.2 v. 13. for all output voltages and -40 c to 85 c overall voltage accuracy is 2.9%. 14. typical disable current is in the na.
ncp590 http://onsemi.com 5 electrical characteristics -40 c t a 85 c (note 5); v in = v out +0.5 v or 2.1 v, whichever is greater (note 6). v en1,2 = 0.95 v, c in = c out1,2 = 1.0 f, unless noted otherwise parameter unit max typ min test conditions symbol regulators ground current; i gnd = i in C i out i gnd v en1 = 0.95 v, i out1 = 200 ma; v en2 = 0.4 v, i out2 = 0 ma or v en2 = 0.95 v, i out2 = 200 ma; v en1 = 0.4 v, i out1 = 0 ma one regulator on; one regulator off - 105 150 a ground current; i gnd = i in C i out i gnd i out1 = i out2 = 200 ma both regulators on - 175 250 a disable current; i dis = i in C i out i dis i out1,2 = 0 ma, v en1,2 = 0.4 v both regulators off 0 (note 14) 1 a i load load current (note 10) i out 0 - - ma maximum output current i out 300 - - ma current limit, per regulator (note 9) i sc v out = 0 v - 750 - ma output noise voltage (note 9) e n bw = 10 hz to 100 khz v out = 0.8 v v out = 2.8 v - - 20 30 - - v rms thermal shutdown (note 9) t jsd junction t emperature - 155 - c hysteresis - 15 - input under voltage lock out uvlo - 1.9 2.1 v uvlo hysteresis uvlo hys - 0.1 - v power supply rejection ratio (note 9) psrr i out = 200 ma 120 hz 0.8 v output 120 hz 1.8 v output 120 hz 2.8 v output - - - 60 55 50 - - - db power supply rejection ratio (note 9) psrr i out = 200 ma 1 khz 2.8 v output - 40 - db enable control characteristics maximum input current at en input i en v en = 0.0 v - 0.01 - a v en = v in - 0.01 - low input threshold v il - - 0.4 v high input threshold v ih 0.95 - - v timing characteristics turn on time delay, both outputs turned on with enable t on to 95% v o v in(min) to 5.5 v - 375 700 s turn off time delay, both outputs turned off with enable (note 9) t off v in = 5.5 v v out = 5 v, to v out = 250 mv v out = 0.8 v, to v out = 40 mv - - 215 155 - - s s recommended output capacitor specifications output capacitance (note 9) c out capacitance over full temperature range of application. any esr 0.7 1.0 4.7 f 5. performance guaranteed over specified operating range by design, guard banded test limits, and/or characterization. productio n tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible . 6. v out based on the greater of the two outputs. 7. overall accuracy specified over specified operating conditions of line, load, and temperature. 8. drop out voltage v do = v in C v out measured when the output voltage has dropped 100 mv from the nominal value for v out > 2.0 v. 9. guaranteed by design, not production tested. 10. regulated and stable output over full load range down to 0 ma load. 11. v in is set at v in = ((v out + 0.5 v) + 5.5 v) / 2 or v in = ((2.1 v) + 5.5 v) / 2, whichever is greater. 12. applicable for v out 1.2 v. 13. for all output voltages and -40 c to 85 c overall voltage accuracy is 2.9%. 14. typical disable current is in the na.
ncp590 http://onsemi.com 6 figure 3. measuring circuit ncp590 v in v in en1 en2 nc on off on off i in c in 1 f i gnd v out1 v out2 gnd nc i out1 i out2 c out1 1 f c out2 1 f v out1 v out2 r load r load
ncp590 http://onsemi.com 7 typical performance characteristics 200 ma 1.0 ma figure 4. current limit vs. temperature figure 5. t ypical output voltage variation vs. load current temperature ( c) load current (ma) 80 60 40 20 0 -20 -40 0 100 200 300 500 600 800 900 300 200 100 0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 figure 6. power supply rejection ratio figure 7. cross channel rejection vs. frequency f, frequency (hz) f, frequency (hz) 10,000 1,000 100 10 0 10 20 30 40 50 60 figure 8. output voltage change vs. temperature for 0.8 v out figure 9. output voltage change vs. temperature for 5.0 v out temperature ( c) temperature ( c) 80 60 40 20 0 -20 -40 0.785 0.790 0.795 0.800 0.805 0.810 0.815 80 60 40 20 0 -20 -40 4.95 4.96 4.97 5.00 5.01 5.02 5.04 5.05 current limit (ma) output droop (%) ripple rejection (db) v out , output voltage (v) v out , output voltage (v) 400 700 200 ma 150 ma 100 ma 50 ma 1 ma 4.98 4.99 5.03 200 ma 150 ma 100 ma 50 ma 1 ma v out = 2.8 v 5.0 v 3.3 v out 2.8 v out 1.5 v out 0.8 v out -60 -50 -40 -30 -20 -10 0 rejection (db) 10 100 1000 10000
ncp590 http://onsemi.com 8 typical performance characteristics figure 10. output voltage change vs. temperature for 2.8 v out figure 11. 2.8 v out vs. line transient temperature ( c) 80 60 40 20 0 -20 -40 2.77 2.79 2.80 2.81 2.82 2.83 figure 12. load transient on 2.8 v out and effect on 2.8 v out for 200 ma step figure 13. load transient on 5.0 v out and effect on 3.3 v out for 200 ma step figure 14. load transient on 0.8 v out and effect on 1.5 v out for 200 ma step figure 15. typical turn-on delay for 3.3 v out 1 ma, 5.0 v out 200 ma output with simultaneous v in and enable v out , output voltage (v) 2.78 200 ma 150 ma 100 ma 50 ma 1 ma ch2 2.8 v output1 200 ma step 50 mv / div ch3 2.8 v output2 1 ma load 10 mv / div ch2, 0.8 v output 200 ma step 50 mv / div ch3 1.5 v output 1 ma load 10 mv / div ch4 200 ma step on 0.8 v output ch2 v in 3.3 v to 3.8 v 1 v / div 30 s rise 30 s fall ch3 2.8 v output, 1 ma load 10 mv / div, 7 mv pk ncp590 2.8 v output, line transient response, dv in = 0.5 v, t rise = t fall = 30 sec. ch3, 5.0 v out 50 mv / div 200 ma step ch2 3.3 v out 10 mv / div 1 ma load ch4 5.0 v out 200 ma step ch3 en1, en2, v in 2 v / div ch2 v out2 2 v / div c2 rise, 50.9 s : 4.80 v : 362 s @: 4.76 v c4 rise 24.3 s ncp590 delay 5.5 v in , en1 = en2 = v in step, v out1 = 3.3 v 1 ma, v out2 = 5.0 v 200 ma ch4 200 ma step on 2.8 v output1, 200 ma / div ch4, v out1 1 v / div
ncp590 http://onsemi.com 9 application information output regulator the output is controlled by a precision trimmed reference and error amplifier. the output has saturation control for regulation while the input voltage is low, preventing over saturation. current limit and voltage monitors complement the regulator design to give safe operating signals to the pro cessor and control circuits. standard linear regulator design circuitry consists of only an active output driver providing current at the regulated voltage with resistors from the regulated output to ground (used in the feedback loop). this provides good turn-on characteristics from the active pfet output driver, but turn-off characteristics are determined by the output capacitor values and impedance of the load in parallel with the internal resistors in the feedback loop. the turn-off time in the situation with high impedance loads will be slow. the ncp590 has active pull-down transistors which turn on during device turn-off creating efficient fast turn-offs independent of loading. stability considerations the input capacitor c in in figure 3 is necessary to provide low impedance to the input of the regulator. the output or compensation capacitor c outx helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25 c to -40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturer's data sheet usually provides this information. stability is guaranteed at values c out = 0.7 f to 4.7 f and any esr within the operating temperature range. calculating power dissipation in a dual output linear regulator the maximum power dissipation for a dual output regulator (figure x) is: p d = (v in C v out1 ) x i out1 + (v in C v out2 ) x i out2 + v in x i gnd (1) where: v in is the maximum input voltage, v out is the output voltage for each output, i out is the output current for each output in the application, and i gnd is the quiescent or ground current the regulator consumes at i out . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja (125 o c t a ) p d (eq. 1) the value of r ja can then be compared with those in the thermal resistance section of the data sheet. those board areas with r ja 's less than the calculated value in equation 2 will keep the die temperature below 125 c. in some cases, none of the circuit board areas will be sufficient to dissipate the heat generated by the ic, and an external heat sink will be required. the current flow and voltages are shown in the measurement circuit diagram. a chart showing thermal resistance vs. pcb heat spreader area is shown below. enable enabling the two outputs is controlled by two independent pins, en1 and en2. a high (above the high input threshold) on these logic level input pins causes the outputs to turn on. normal operation allows for input voltages to these pins to 0.3 v above v in . it is sometimes necessary to interface logic outputs from different operating voltages into these pins. this happens when standard operating system voltages must interface together (i.e., 5 v to 3.3 v systems). for example, a 5 v control voltage is needed to control the ncp590 operating with v in = 3.6 v. the input current into the enx pin can be kept to safe levels by adding a 100 k resistor in series with the 5 v control drive voltage. this will keep the input voltage in compliance with the maximum ratings and will allow control of the output. use of this setup will affect turn-on time and will increase the enable current higher than the input current specified in the electrical parameter tables.
ncp590 http://onsemi.com 10 figure 16. thermal performance on pcb heat spreader copper heat spreading area (mm 2 ) ja ( c/w) 400 350 300 200 150 100 250 50 0 650 600 550 500 450 400 350 300 250 200 150 100 50 0 1 oz 2 oz thermal impedance of the ncp590 dfn8 mounted to a single sided copper plated circuit board. ordering information* device output v oltage package shipping orderable part number marking code v out1 v out2 ncp590mnvvtag vv 3.3 3.3 dfn8 2x2 10,000 / tape & reel ncp590mnpptag pp 2.8 2.8 dfn8 2x2 10,000 / tape & reel ncp590mndptag dp 1.8 2.8 dfn8 2x2 10,000 / tape & reel ncp590mnoatag oa 1.5 2.4 dfn8 2x2 10,000 / tape & reel NCP590MN5DTAG 5d 1.2 1.8 dfn8 2x2 10,000 / tape & reel ncp590mn5atag 5a 1.2 1.5 dfn8 2x2 10,000 / tape & reel *contact factory for additional voltage combinations.
ncp590 http://onsemi.com 11 package dimensions dfn8, 2x2 case 506aa-01 issue d notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 . 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? ??? a d e b c 0.10 pin one 2 x reference 2 x top view side view bottom view a l (a3) d2 e2 c c 0.10 c 0.10 c 0.08 8 x a1 seating plane e/2 e 8 x k note 3 b 8 x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k 0.20 --- l 0.25 0.35 1 4 8 5 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 ncp590/d literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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